1. Field of the Invention
The present invention relates generally to a semiconductor technique and more particularly to a silicone-containing dielectric film having good filling or padding property for an interconnect structure of a semiconductor substrate.
2. Description of the Related Art
The requirements for semiconductor processing technologies are increasing as the device nodes continue to become smaller, and the requirements for hard masking are also getting higher to improve the processing performance from dry etching. Also, conventional film forming technologies cannot form desired insulation films in STI and Bit lines, etc., and therefore improvements, modifications and new process applications are being examined.
High-density plasma CVD that provides filling characteristics was first applied to 250-nm node devices, after which the technology was applied to wiring and passivation processes of various devices. As the device node decreased, efforts were made to improve the film quality and the technology became the standard in the application of embedded oxide films in PMD and STI processes. When the device node became smaller than 130 nm, however, it became difficult to meet the need for fully-filling in STI processes with high-density plasma CVD, and therefore other technologies were adopted such as raising the bottom of the STI structure with a coating material and then filling a film using high-density plasma CVD. At the same time, measures are being taken to improve the film forming and etching technologies based on high-density plasma CVD in order to meet the required filling characteristics.
Since the reduction in width increases the aspect ratio, use of high-density plasma CVD is also becoming difficult in PMD processes.
Now that device nodes smaller than 50 nm are available, STI openings have become smaller than 30 nm and PMD sizes have dropped to less than 50 nm, and accordingly new filling technologies are needed. As specific methods, forming technologies using coating materials, film forming technologies using thermal CVD with O3, combined technologies using a combination of multiple films, and technologies that use siloxane reaction via plasma CVD have been evaluated. In STI processes, the maximum temperature is high, or around 800 to 1,000° C., and thus the gases released from the embedded film react inside the film and dissociate from the film, which results in a space film structure. Also in the chemical solution step performed after the CMP step in the STI process, fluorinated gases are used and thus the embedded film must be resistant to wet etching. Films that become sparse after heat treatment allow chemical solutions to permeate quickly. This leads to a higher etch rate, and the rate may become different in each location of the film embedded in the STI structure. It has been shown that, when siloxane reaction is used, voids inevitably generate during heat treatment because of the OH bond in the film, and consequently the wet resistance and other properties decrease.